Phase locking loops (PLLs) are well known circuits with a number of applications. A primary application of PLLs is in frequency synthesis, where a high frequency signal is generated from a much lower reference frequency. The frequency of the generated signal is determined by the value of a multiplier. For example, an input reference frequency of 1 MHz can be multiplied by 2000 to produce a 2000 MHz output signal. The value of the multiplier can be easily changed thus allowing the frequency of the output signal from the frequency synthesiser to be changed easily. This means that the frequency of the output signal can be changed quickly.
However, such frequency synthesisers suffer from drawbacks, particularly where it is necessary or desirable to change the output frequency thereof quickly. This problem can be better understood by considering the example of FIG. 1, which shows a block diagram of a known part of a demodulator 2 such as superheterodyne receiver. The demodulator 2 includes an antenna 4, arranged to receive radio frequency signals which are bandpass filtered by a BPF 6, amplified by a low noise amplifier 8 and then mixed at mixer 12 with a variable frequency from a frequency synthesiser 10 such that the mixer output is a fixed intermediate frequency (IF). In order to maintain the fixed IF as the frequency of the received RF signals changes, the frequency synthesiser 10 must change its output accordingly. For a PLL frequency synthesiser, this in turn requires a change in the frequency multiplier.
The frequency change is typically carried out via the PLL, and a schematic PLL is shown in FIG. 2. This well-known arrangement includes a voltage controlled oscillator 22, a divider 24, a phase detector 26 fed with a reference (clock) signal, and a loop filter 28.
The VCO 22 produces the output signal of the frequency synthesiser 10. This output is fed back also to the divider 24 whose output is a signal in phase with the VCO output signal but at a frequency which is (1/N) of the VCO output frequency. Both the reference signal and divided VCO output are input to a phase detector 26 which generates an output related to the phase difference (if any) between the VCO output signal and an input reference signal (REF). The phase error signal is filtered by the loop filter 28 and fed to the VCO input which causes adjustment of the output thereof in dependence upon the phase difference input. Thus, the output of the VCO 22 locks onto N times the reference frequency, REF.
The open loop s-domain transfer function of the frequency synthesiser 10 shown in FIG. 2 is                                           K            VCO                    ⁢                      K            PD                    ⁢                      LF            ⁡                          (              s              )                                      N                            (        1        )            
where KVCO is the gain of the VCO 22;
KPD is the gain of the phase detector 26;
LF(s) is the s-domain transfer function of the loop filter including the VCO 22 and the phase detector 26; and
N is the multiplier.
As can been seen from equation (1), as the value of the multiplier N changes, the open loop s-domain transfer function of the frequency synthesiser changes. FIG. 3a shows a schematic plot (in the upper part) of DC gain of the loop transfer function vs. frequency. The lower part shows the phase margin as a function of frequency. As is seen in FIG. 3a, the gain vs. frequency function changes from the solid line 34 where N=N1 to the dotted line 32 where N=N2, N2 being less than N1.
The frequency at which the DC gain passes through zero is the frequency at which the phase margin is measured for a given N. So, for N1 (given by the solid line 34 in FIG. 3a), the phase margin is at a maximum given by Ø1. As N1 changes to N2, to produce the gain vs. frequency plot 32 (dotted line), the phase margin decreases to Ø2. The phase margin is a measure of the speed at which the frequency synthesiser 10 settles to an output frequency and is determined by the characteristics of the loop filter 28. The net result of this is that the phase margin has a maximum for a particular value of N (in this example, N1,) and decreases for N=N1. A PLL can be designed to have a minimum settling time i.e. phase margin for a most convenient value of N but this necessarily means a degradation in time to lock as different values of N are required, i.e. different output frequencies.
FIG. 3b shows a graph 40 of frequency response against time for the known frequency synthesiser 10. The step response 42 shows an ideal frequency characteristic, where, as the value of N changes from N1 to N2, the output frequency of the frequency synthesiser instantly changes from f1 to f2. However, due to the deterioration in phase margin as N1 changes to N2 (FIG. 3a), the actual response of the frequency synthesiser 10 would be similar to the underdamped response 44 or the overdamped response 46.
The lower the phase margin, the longer the time taken for the frequency response to settle to a desired frequency 42 output.
Such a settling period can present serious difficulties when fast settling is necessary, for example in wireless local area networks (WLANs).
It is therefore an object of the present invention to address this problem.